module StateMachine(
    input   wire            clk     ,
    input   wire            clr     ,
    input   wire            start   ,
    input   wire            step2   ,
    input   wire            step3   ,
    output  wire    [2:0]   out      
);

parameter   STATE0 = 4'b0001,
            STATE1 = 4'b0010,
            STATE2 = 4'b0100,
            STATE3 = 4'b1000;

reg [3:0] state;
reg [3:0] state_next;

// 状态迁移
always @(posedge clk) begin 
    if(clr) begin 
        state <= STATE0;
    end
    else begin 
        state <= state_next;
    end
end

// 次态逻辑 
always @(*) begin 
    case(state) 
    STATE0: state_next = start ? STATE1 : STATE0;
    STATE1: state_next = STATE2; 
    STATE2: state_next = step2 ? STATE3 : STATE0;
    STATE3: state_next = step3 ? STATE0 : STATE3;
    default: state_next = STATE0;
    endcase
end

// 输出逻辑 
assign out = (state == STATE0) ? 3'b001 : 
             (state == STATE1) ? 3'b010 : 
             (state == STATE2) ? 3'b100 : 
             (state == STATE3) ? 3'b111 : 3'b000;

endmodule